Bringing Formal Property Verification Methodology to SoC Interconnects

With many system bus alternatives in telecom, signal processing, etc, chip designers face the prospect of having to support multiple interfaces to meet interconnect requirements. Designers must then build next-generation chip architectures that deliver reliable interconnect architectures and ensure interworking between SoC heterogeneous IP blocks. In this article we show how formal verification associated with assertions can help and automate the functional verification of SoC interconnects, and particularly bridges: transactions translation checking, functional performance analysis, address/data consistency checking. With our proposed methodology, these tasks can bring more automation and robustness to the functional verification of SoC interconnects.